1. Field of the Invention
The present invention relates to a plasma display panel, and more particularly, to a method for driving a plasma display panel.
2. Description of the Background Art
A plasma display panel (hereinafter, referred to as a ‘PDP’) is adapted to display an image by light-emitting phosphors with ultraviolet rays generated during the discharge of an inert mixed gas such as He+Xe, Ne+Xe or He+Ne+Xe, or the like. This PDP can be easily made thin and large, and it can provide greatly increased image quality with the recent development of the relevant technology.
Referring now to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a scan electrode 30Y and a sustain electrode 30Z which are formed on the bottom surface of an upper substrate 10, and an address electrode 20X formed on a lower substrate 18. Each of the scan electrode 30Y and the sustain electrode 30Z include transparent electrodes 12Y and 12Z, and metal bus electrodes 13Y and 13Z which have a line width smaller than that of the transparent electrodes 12Y and 12Z and are respectively disposed at one side edges of the transparent electrodes. The transparent electrodes 12Y and 12Z, which are generally made of ITO (indium tin oxide), are formed on the bottom surface of the upper substrate 10. The metal bus electrodes 13Y and 13Z, which are generally made of metal such as chromium (Cr), are formed on the transparent electrodes 12Y and 12Z, and serves to reduce a voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance.
On the bottom surface of the upper substrate 10 in which the scan electrode 30Y and the sustain electrode 30Z are placed parallel to each other, is laminated an upper dielectric layer 14 and a protective layer 16. The upper dielectric layer 14 is accumulated with a wall charge generated during plasma discharging. The protective layer 16 is adapted to prevent damages of the upper dielectric layer 14 due to sputtering caused during plasma discharging, and improve efficiency of secondary electron emission. As the protective layer 16, magnesium oxide (MgO) is generally used.
A lower dielectric layer 22 and a barrier rib 24 are formed on the lower substrate 18 in which the address electrode 20X is formed. A phosphor layer 26 is applied to the surfaces of both the lower dielectric layer 22 and the barrier rib 24. The address electrode 20X is formed in the direction of crossing the scan electrode 30Y and the sustain electrode 30Z. The barrier rib 24 is disposed in parallel with the address electrode 20X and prevents ultraviolet rays and visible lights to be caused during plasma discharging from getting leaked to an adjacent discharge cells. The phosphor layer 26 is excited with an ultraviolet ray generated during the plasma discharging to generate any one visible light of red, green and blue lights. An inert mixed gas is injected into the discharge spaces defined between the upper substrate 10 and the barrier ribs 24 and between the lower substrate 18 and the barrier ribs 24.
In this PDP, one frame is divided into a plurality of sub-fields which having different luminance frequencies and is driven with time division, thereby implementing the gradation of image. Each of sub-fields are divided into an initialization period for initializing an entire screen, an address period for selecting an address line and selecting a cell from the selected address line, and a sustain period for implementing gradation of image in response to the luminance frequency. Herein, the initialization period consists of a setup period which provided with a rising ramp waveform and a setdown period which provided with a falling ramp waveform.
For example, when displaying an image with 256-level gray scale, a period (16.67 ms) of one frame that corresponds to 1/60 second is divided into eight sub-fields (SF1 to SF8), as shown in FIG. 2. Each of the eight sub-fields (SF1 to SF8) consists of the initialization period, the address period, and the sustain period, as mentioned above. The initialization periods and the address periods of each of the sub-fields have equal intervals. But the sustain periods of each of the sub-fields have increasing intervals in the ratio of 2n (n=0, 1, 2, 3, 4, 5, 6, 7).
FIG. 3 shows a driving waveform of PDP which provided to two sub-fields.
In FIG. 3, Y indicates a scanning electrode and Z indicates a sustain electrode, and X indicates an address electrode.
Referring to FIG. 3, a PDP is driven with a reset period for initializing an entire screen and an address period for selecting a cell, and a sustain period for maintaining the discharge of the selected cell.
In the reset period, a rising ramp waveform (Ramp-up) is applied to all scanning electrodes Y during a setup period. This rising ramp waveform (Ramp-up) makes the cells of the entire screen to generate a weak discharge, thereby forming a wall charge in the cells. In the setdown period, after being provided with the rising ramp waveform (Ramp-up), a falling ramp waveform (Ramp-down) which is falling in the positive polarity lower than a peak voltage of the rising ramp waveform (Ramp-up) is applied to the scanning electrodes Y, simultaneously. The falling ramp waveform (Ramp-down) makes the cells to generate a weak discharge, so that an unnecessary charge of wall charge and space charge generated by the setup discharge may be removed and a wall charge which is necessary for address discharge in the cells of the entire screen may be remained uniformly.
In the address period, scan pulses (scan) of a negative polarity are sequentially applied to the scanning electrodes Y, and in the same time, data pulses (data) of positive polarity are applied to the address electrodes X. A voltage difference between the scan pulses (scan) and the data pulses (data) is added to the wall charge generated during the initialization period, so that an address discharge may be generated in the cells to which the data pulses (data) are applied. Therefore, a wall charge generates in the cells selected by the address discharge.
On the other hand, during the setdown period and the address period, the sustain electrodes Z is provided with a DC voltage of positive polarity having a sustain voltage level Vs.
In the sustain period, sustain pulses (sus) are alternatively applied to the scanning electrodes Y and the sustain electrodes Z. Then, the cells selected by the address discharge are added with the wall voltage and sustain pulses (sus) in the cells, so that a sustain discharge may be generated in the form of surface discharge between the scanning electrode Y and the sustain electrode Z whenever the application of the sustain pulses (sus). Finally, after completion of the sustain discharge, the sustain electrode Z is supplied with an erasing ramp waveform (erase) having small pulse width, and the wall charge in the cells is erased the erasing ramp waveform.
However, the conventional PDPs have problems in that a discharge efficiency become lower by the wall charge to be formed in the address electrode X. More specifically, the address electrodes X maintains a base potential during the sustain period that the sustain pulses is alternatively supplied to the scanning electrodes Y and the sustain electrodes Z.
Herein, the address electrodes X maintaining the base potential are accumulated with predetermined wall charges generated from the sustain discharge. This wall charges causes the sustain discharge having a low luminance efficiency. In practical, the wall charges formed in the address electrodes X have a wall voltage that is equal to around half voltage of the sustain pulses.
In order to solve this problem, it has proposed that the address electrodes X are supplied with a DC voltage of positive polarity having an address voltage level Va during a sustain period, as shown in FIG. 4. When the address electrodes X are supplied with the DC voltage of positive polarity during the sustain period, the wall charges generated in the address electrodes X become minimized, the driving efficiency becomes higher, accordingly. In other words, a stable sustain discharge is achieved by lowering the wall voltage of the wall charges formed in the address electrodes X. Practically, it has experimentally proved that the driving efficiency of PDP is improved when the address electrodes X had been supplied with the DC voltage of positive polarity during the sustain period.
However, a driving method shown in FIG. 4 has a problem that an erroneous discharge is generated when there are both a selective write subfield and a selective erase sub-field. Referring to FIG. 5, the selective erase sub-fields are consisted of the address period and the sustain period, thus the address discharge of the address period is followed immediately after completion of the sustain period. Herein, in order to higher the driving efficiency, if the address electrodes X is supplied with the DC voltage of positive polarity having the address voltage level during the sustain period in the sub-fields before beginning of the selective erase sub-fields, a discharge condition is changed. Therefore, an amount of the wall charges of positive polarity which is accumulated in the address electrodes X may be decreased accordingly, and in the subsequent address period, the amount of the wall voltage in the address electrodes X becomes insufficient, thereby generating an erroneous discharge.